Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily doped source/drain structures 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). The source/drain structures 105, illustrated in FIG. 1, are lightly-doped-drain (LDD) structures. Each LDD structure includes a lightly-doped, lower conductivity region 106 (hereinafter referred to as LDD region) near the channel region 107 and a heavily-doped, higher conductivity region 104 (hereinafter referred to as source/drain region) typically connected to the source/drain terminal. As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain structure refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain structure 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain structure 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain structure 105 or channel region 107.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
One important step in the manufacture of MOS devices is the formation of the gate electrode and source/drain structures. These structures are typically formed by first depositing, usually through chemical vapor deposition (CVD), a layer of polysilicon over the entire substrate. The polysilicon layer is then patterned using a mask and etched, typically through a dry etch process, to form the gate electrode. An LDD implant is then performed to form the LDD regions 106. Spacers 108 are then formed on the gate electrode 103. Using the spacers for alignment, a source/drain implant is performed to form the source/drain regions 104 and to dope the gate electrode 103. The substrate 101 is then annealed to activate the dopants in the source/drain structures 105 as well as the dopant in the gate electrode 103.
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) in order to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be altered. The depth of the source/drain region is an important dimension which must be scaled down as the device structure is made smaller. However, as the source/drain junction depth is reduced, complexities arise in the fabrication process.